Low-power FPGA implementation for DA-based video processing

In this paper, we propose a low-power distributed arithmetic (DA) -based method specifically for the field programmable field array (FPGA) implementation of video processing systems. By taking advantage of the correlation of the input data and using a parallel structure, the FPGA implementation of a convolution example based on the proposed method requires only 75% of power while maintaining the same throughput compared to the existing method of J.T. Ludwig, et al. (1996) and R. Amirtharajah, et al. (1999) . The proposed method can be applied to many video processing applications such as discrete cosine transform, discrete wavelet transform, discrete Fourier transform and motion estimation.