A low power high performance distributed DCT architecture

Author

Shams, Ahmed ; Pan, Wendi ; Chidanandan, Archana ; Bayoumi, Magdy A.

fYear

2002

fDate

2002

Firstpage

21

Lastpage

27

Abstract

A new distributed arithmetic architecture, NEDA, is presented in this paper. NEDA is a low power optimized architecture based on the distributed arithmetic paradigm. In addition to low power performance, NEDA offers high speed and reduced area. In NEDA, inner product computational module has been proved, mathematically, to require only additions. Moreover, minimum number of additions is used by exploiting the redundancy in the adder array. Such properties have made a NEDA unit a basic computational module for high performance DSP architectures. A case study of 8×8 DCT NEDA-based architecture is analyzed. Savings exceeding 88% are achieved for the DCT implementation

Keywords

VLSI; adders; discrete cosine transforms; distributed arithmetic; low-power electronics; redundancy; NEDA; VLSI; adder array; distributed DCT architecture; distributed arithmetic architecture; inner product computational module; low power optimized architecture; new distributed architecture; redundancy; Arithmetic; Computer architecture; Digital signal processing; Digital signal processing chips; Discrete cosine transforms; Distributed computing; Hardware; High performance computing; Read only memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on

Conference_Location

Pittsburgh, PA

Print_ISBN

0-7695-1486-3

Type

conf

DOI

10.1109/ISVLSI.2002.1016869

Filename

1016869