A universal test structure for the direct measurement of the design margin of even-stage ring oscillators with CMOS latch

Author

Hirakawa, Yutaka ; Motomura, Ayami ; Ota, Kohei ; Mimura, Norihiro ; Nakamura, Kazuyuki

Author_Institution

Center for Microelectron. Syst., Kyushu Inst. of Technol., Iizuka, Japan

fYear

2012

fDate

19-22 March 2012

Firstpage

18

Lastpage

22

Abstract

To validate our optimized design theory for Even Stage Ring Oscillators (ESROs), we have developed a Universal ESRO TEG (U-ESRO TEG) constructed with Equivalent Variable-W Transistors (EVWTs) and Initial-voltage Preset-able Inverters (IPIs). The design parameters can be changed with a single circuit, and it is possible to measure the operation margin and oscillation availability of an ESRO. Experimental results confirm the validity of our ESRO design theory.

Keywords

CMOS logic circuits; flip-flops; integrated circuit testing; invertors; oscillators; CMOS latch; ESRO oscillation availability; EVWT; IPI; equivalent variable-W transistors; even-stage ring oscillator design margin; initial-voltage preset-able inverters; optimized design theory; universal ESRO TEG; universal test structure; CMOS integrated circuits; Inverters; Latches; Pins; Random access memory; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2012 IEEE International Conference on

Conference_Location

San Diego, CA

ISSN

1071-9032

Print_ISBN

978-1-4673-1027-7

Type

conf

DOI

10.1109/ICMTS.2012.6190605

Filename

6190605