Energy efficient design of direct coupled pass transistor based pulse triggered flip-flop

This paper presents a high performance, energy efficient implicit pulsed triggered flip flop based on direct coupled pass transistor (DCPT) approach. This approach directly couple input D to output Q of the flip flop to alleviate the worst case delay. It reduces input to output travelled path hence reduces D-to-Q delay and power consumption. It also includes an extra NMOS for latch designing to reduce the crossbar current. The simulation results presented are obtained by using SAED90nm CMOS technology with supply voltage 1V at 25°C temperature. It operates at 500MHz of clock frequency. By this technique it improves D-to-Q delay by 2% and power-delay-product by 22% for the proposed implicit pulsed flip flop.