DocumentCode
1941726
Title
A 2D Carrier Profiling Technique for VLSI Planar Structures
Author
Hill, C. ; Pearson, P.J. ; Lewis, B ; Holden, A.J. ; Allen, R W
Author_Institution
Plessey Research Caswell Ltd., Caswell, Towcester, Northants., England, NN12 8EQ
fYear
1987
fDate
14-17 Sept. 1987
Firstpage
923
Lastpage
926
Abstract
A novel technique for obtaining two-dimensional free carrier profiles with high spatial resolution has been developed. The technique involves fully automated anodic sectioning of resistor structures on a special VLSI test chip and computer analysis of the data. Application of the technique to determination of the 2D distribution of boron in silicon under an oxide mask edge after implant and anneal is described, and results at a spatial resolution of 600Ax600A and sensitivity of 1017 ions/cc are presented.
Keywords
Annealing; Application software; Automatic testing; Boron; Data analysis; Implants; Resistors; Silicon; Spatial resolution; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1987. ESSDERC '87. 17th European
Conference_Location
Bologna, Italy
Print_ISBN
0444704779
Type
conf
Filename
5436777
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