Design and performance of the low noise cascode IC for wireless applications

Author

Dåbrowski, Jerzy ; Nosal, Zbigniew ; Abramowicz, Adam ; Adamski, Miroslaw ; Leblanc, Remy ; Dupont, Giles

Author_Institution

Ericsson AB, Stockholm, Sweden

Volume

3

fYear

2004

fDate

17-19 May 2004

Firstpage

882

Abstract

The paper presents the design and test results of a novel low noise cascade amplifier IC for applications in the GSM and WCDMA base station receivers. The selection of transistor geometry to minimize noise figure and the factors affecting the intermodulation properties are discussed. Stability of the cascade circuit and the interaction with the package is examined and the guidelines for optimum design are formulated. The resulting CGY2J07 dual cascade chip manufactured by OMMIC demonstrates minimum noise figure NFmin = 0.35 dB in the 2 GHz band and in a balanced amplifier configuration provides > 23 dB gain with the input IP3 value of 9 dBm and NF below 0.7 dB. This is the only chip currently available on the market with this level of performance.

Keywords

broadband networks; cellular radio; code division multiple access; integrated circuit design; integrated circuit testing; intermodulation distortion; radio receivers; radiofrequency amplifiers; radiofrequency integrated circuits; transistors; 0.35 dB; 2 GHz; CGY2J07 dual cascade chip; GSM base station receiver; WCDMA base station receiver; cascode LNA integrated circuit; intermodulation distortion; intermodulation property; low noise cascade amplifier IC; noise figure; transistor geometry; Application specific integrated circuits; Base stations; Circuit testing; GSM; Geometry; Integrated circuit noise; Integrated circuit testing; Low-noise amplifiers; Multiaccess communication; Noise figure;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwaves, Radar and Wireless Communications, 2004. MIKON-2004. 15th International Conference on

Print_ISBN

83-906662-7-8

Type

conf

DOI

10.1109/MIKON.2004.1358504

Filename

1358504