Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems

Author

Tomabechi, Nobuhiro

Author_Institution

Hachinohe Inst. of Technol., Japan

fYear

1989

fDate

2-4 Oct 1989

Firstpage

362

Lastpage

365

Abstract

A counter-based residue arithmetic circuit composed of ring counters which performs residue arithmetic operations by pulse counting is proposed for easily testable VLSI digital signal processing systems. A master-slice LSI on which counter-based residue arithmetic circuits are regularly arranged is also presented. It is demonstrated that the counter-based residue arithmetic circuit has a self-testable structure, and a highly regular and easily testable system implementation can be realized using the circuits

Keywords

VLSI; cellular arrays; counting circuits; digital arithmetic; digital signal processing chips; integrated circuit testing; counter-based residue arithmetic circuit; easily testable VLSI digital signal processing systems; highly regular; master-slice LSI; pulse counting; residual number system; residue arithmetic operations; ring counters; self-testable structure; Built-in self-test; Circuit testing; Counting circuits; Digital arithmetic; Digital signal processing; Large scale integration; Performance evaluation; Pulse circuits; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-1971-6

Type

conf

DOI

10.1109/ICCD.1989.63388

Filename

63388