GaAs 10 K gates gate array with digital variable delay macro cell

Author

Ohta, A. ; Higashisaka, N. ; Shimada, M. ; Heima, T. ; Hosogi, K. ; Ohmura, R. ; Tanino, N.

Author_Institution

Optoelectron. & Microwave Devices R&D Lab., Mitsubishi Electr. Corp., Hyogo, Japan

fYear

1995

fDate

Oct. 29 1995-Nov. 1 1995

Firstpage

323

Lastpage

326

Abstract

A GaAs 10 K gates gate array with digital variable delay macro cell is successfully developed for various measurement instrument applications. The digital delay circuit has 38.8 ns span and 50 ps resolution, and power dissipation is 300 mW, which is about half the dissipation for conventional analog delay circuits. It is possible for the gate array to include up to 8 delay macro cells with 800 gates. The gate array is fabricated using 0.5 /spl mu/m BPLDD (Buried p-layer Lightly Doped Drain) SAGFET (self-align gate metal FET) technology with triple metal layers. This chip is packed in a 132 pin ceramic QFP (quad flat package).

Keywords

III-V semiconductors; cellular arrays; delay circuits; field effect logic circuits; gallium arsenide; large scale integration; logic arrays; 0.5 micron; 300 mW; 38.8 ns; 50 ps; BPLDD; GaAs; SAGFET; buried p-layer; ceramic QFP; digital delay circuit; digital variable delay macro cell; gate array; lightly doped drain; measurement instrument applications; quad flat package; self-align gate metal FET; triple metal layers; Clocks; Counting circuits; Delay effects; Frequency; Gallium arsenide; Instruments; Linearity; Power dissipation; Signal generators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1995. Technical Digest 1995., 17th Annual IEEE

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-2966-X

Type

conf

DOI

10.1109/GAAS.1995.529021

Filename

529021