Compact modeling of stress effects in scaled CMOS

Author

Chi-Chao Wang ; Wei Zhao ; Liu, F. ; Min Chen ; Yu Cao

Author_Institution

Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA

fYear

2009

fDate

9-11 Sept. 2009

Firstpage

1

Lastpage

4

Abstract

Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90 nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (L_sd). In this work, a compact model that physically captures these behaviors is developed for circuit simulation with strained CMOS technology.

Keywords

CMOS integrated circuits; carrier mobility; circuit simulation; elemental semiconductors; integrated circuit modelling; nanoelectronics; silicon; stress effects; MOSFET; Si; carrier mobility; carrier transport; channel length; circuit simulation; compact model; layout parameters; nonuniform stress distribution; scaled CMOS; source-drain diffusion length; strained silicon; stress effects; CMOS process; CMOS technology; Capacitive sensors; Circuit simulation; Effective mass; Laboratories; Scattering; Semiconductor device modeling; Stress; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on

Conference_Location

San Diego, CA

ISSN

1946-1569

Print_ISBN

978-1-4244-3974-8

Type

conf

DOI

10.1109/SISPAD.2009.5290231

Filename

5290231