A fault simulation method based on stem regions

The concept of stem regions has been used as a framework for a fast fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis, for single-output as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. Both the static and dynamic reductions are fully compatible with the parallel pattern evaluation technique, resulting in a very efficient implementation. The simulation algorithm is described, and experimental results for well-known benchmark circuits are shown.<>