Electromigration behavior of flip-chip solder bumps subjected to RF stressing

A test system was built to evaluate RF electromigration characteristics of solder interconnections. The test system measured DC resistance and RF insertion loss and testing was done with high frequency RF signals superimposed on 0 A, 0.25 A or 0.5 A of DC current at elevated temperatures. The test vehicle consisted of daisy chain test Si die with Sn0.7Cu flip chip bumps on 11 mum of plated Cu/Cu/TiW UBM and GaAs die with Sn2.5Ag flip chip bumps on 2 mum plated Ni/Ti UBM. RF stressing resulted in brittle intermetallic structures on the surface of the solder bumps, which is not seen with pure DC stressing. Furthermore, the RF energy created damage through electromagnetic induction current on neighboring unstressed bumps. The superimposition of a 0.5 A DC current on the RF signal accelerated the bump damage rate. In this paper a description of the daisy chain test vehicle, factors considered in RF electromigration testing, variation of DC resistance and RF insertion loss with time, failure analysis using cross-sections and SEM will be used to explain the effect of RF stressing on solder bump behavior.