Faults diagnosis methodology for the WaferNet interconnection network

In this paper, the interconnection network (WaferNet) which is part of an active and reconfigurable prototyping board, named WaferBoardtrade, is analyzed to derive efficient defect diagnosis. The WaferNet structure spans an entire silicon wafer that inevitably contains defects, due to the nature of the microfabrication process, and defect management strategies are inserted in the design flow. Defects must be accurately located to efficiently reconfigure the circuit around them. Key differences between a conventional printed circuit board and WaferNet justify the proposed diagnosis methodology. A sequential walking-one algorithm and a broadcast algorithm are proposed to locate shorts or stuck-at faults in the network. It is shown that dedicated hardware architectures must be integrated in the network to locate those defects in a reasonable time. Analysis shows that the proposed diagnosis time complexity is O(n²), where n is the number of cells in the matrix. An upper bound time limit is calculated that depends on both the size and the number of faults in the circuits.