Fast prototyping based on generic and synthesizable VHDL models. A case study: punctured Viterbi decoders

The increasing complexity of VLSI circuits and the need to reduce the time-to-market, highlight the importance of developing design methodologies capable of solving the problems of fast-prototyping and design-time reduction with a high degree of reliabilty. Within this framework, this paper aims to present a generator-oriented methodology adapted for specific telecommunications functions. This methodology is based on a co-design and unified framework. On the one hand, the system can be specified and optimized. On the other hand, the resulting system specifications can be mapped directly onto a hardware architecture debugged once and for all. This approach thus allows a direct, rapid and safe transition from specifications to prototype. As a case study, we have chosen the Viterbi decoder for punctured codes. This is a generic channel decoding function in wide use in today´s digital communications systems (GSM, Digital Audio/Data Broadcasting (DAB/DDB), Digital TV, (DVB) ADSL and so-on)