• DocumentCode
    1945958
  • Title

    Development of 3D silicon module with TSV for system in packaging

  • Author

    Navas Khan ; Rao, V. Srinivasa ; Samule Lim ; Ho Soon We ; Lee, Victor ; Zhang Xiao Wu ; Yang Rui ; Liao Ebin

  • Author_Institution
    Inst. of Microelectron. (IME), Singapore
  • fYear
    2008
  • fDate
    27-30 May 2008
  • Firstpage
    550
  • Lastpage
    555
  • Abstract
    Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.
  • Keywords
    elemental semiconductors; flip-chip devices; heating; integrated circuit bonding; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; lead bonding; multichip modules; silicon; system-in-package; 3D silicon module; 3D two-stack silicon module; Si; backgrinding; flip chip interconnection; power distribution design; reliability; silicon carrier; system in packaging; temperature cycling; thermo-mechanical analysis; via-first approach; wirebond interconnection; Design optimization; Electronic packaging thermal management; Integrated circuit interconnections; Performance analysis; Power system interconnection; Radio frequency; Silicon; Testing; Thermomechanical processes; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-2230-2
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2008.4550027
  • Filename
    4550027