• DocumentCode
    1946598
  • Title

    CAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filters

  • Author

    Mahram, Atabak ; Herbordt, Martin C.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Boston Univ., Boston, MA, USA
  • fYear
    2012
  • fDate
    29-31 Aug. 2012
  • Firstpage
    217
  • Lastpage
    223
  • Abstract
    BLAST is a central application in bioinformatics and so has been the subject of numerous acceleration studies. The de facto standard version of this code, NCBI BLAST, uses complex heuristics which make it challenging to simultaneously achieve both high performance and exact agreement with the original output. In previous work, we have used novel FPGA-based filters that reduce the input database by over 99.99% without loss of sensitivity. In the present work there are two primary contributions. The first is a new mechanism to couple two of the filters in such a way that promising alignments can be found in a fraction of the previous time. The second is the pipelining of the three filters. This is a challenging load balancing problem since the work per filter drops by 5× - 10× at both of the interfaces. Pipelining the filters has two benefits: it removes the need to reconfigure between passes and it reduces the off-chip bandwidth requirement. Together, these two enhancements more than double the performance over the previous best implementation. We currently have CAAD BLASTP working on Virtex-6 and Stratix-IV FPGAs with speed-ups of 9× and 15×, respectively, over the multithreaded original code running on an 8-core PC. We discuss FPGA features that cause this performance disparity. CAAD BLASTP scales easily and is appropriate for use in large FPGA-based servers.
  • Keywords
    bioinformatics; field programmable gate arrays; information filtering; multi-threading; performance evaluation; pipeline processing; resource allocation; 8-core PC; CAAD BLASTP 2.0; FPGA-based filters; NCBI BLASTP; Stratix-IV FPGA; Virtex-6 FPGA; bioinformatics; de facto standard version; input database reduction; large FPGA-based servers; load balancing problem; multithreaded code; off-chip bandwidth requirement reduction; performance disparity; pipelined filters; Acceleration; Biology; Databases; Field programmable gate arrays; Servers; Standards; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
  • Conference_Location
    Oslo
  • Print_ISBN
    978-1-4673-2257-7
  • Electronic_ISBN
    978-1-4673-2255-3
  • Type

    conf

  • DOI
    10.1109/FPL.2012.6339184
  • Filename
    6339184