A low power capacitive coupled bus interface based on pulsed signaling

Author

Kim, Jongsun ; Choi, Jung-Hwan ; Kim, Chang-Hyun ; Chang, M. Frank ; Verbauwhede, Ingrid

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

35

Lastpage

38

Abstract

A synchronous pulsed signaling system, using on-chip capacitive coupling, for low-power high-speed buses has been implemented in a 0.10-μm CMOS DRAM process. We demonstrate 1.0-Gb/s/pair differential pulsed signaling over 10-cm PCB lines with an increased channel 3-dB bandwidth of 2.94 GHz by blocking the driver/receiver capacitances on a bus and eliminating ESD structures. The system dissipates 1.92 mW for both the driver and channel termination at 500 MHz and 1.8-V supply, which is only 1/8 to 1/13 of conventional memory buses using SSTL-2 and RSL.

Keywords

CMOS integrated circuits; coupled circuits; driver circuits; low-power electronics; pulse circuits; system buses; telecommunication links; 0.10 micron; 1.0 Gbit/s; 1.8 V; 1.92 mW; 10 cm; 2.94 GHz; 500 MHz; CMOS DRAM process; capacitive coupling; channel termination; differential pulsed signaling; driver; driver/receiver capacitance blocking; high-speed buses; low power capacitive coupled bus interface; memory buses; synchronous pulsed signaling system; Bandwidth; Capacitance; Clocks; Coupling circuits; Electrostatic discharge; Packaging; Pulse circuits; Random access memory; Signal design; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358727

Filename

1358727