DocumentCode
1947318
Title
Delay-insensitive carry-lookahead adders
Author
Cheng, Fu-Chiung ; Unger, Stephen H. ; Theobald, Michael ; Cho, Wen-Chung
Author_Institution
Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
fYear
1997
fDate
4-7 Jan 1997
Firstpage
322
Lastpage
328
Abstract
Integer addition is one of the mast important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a delay insensitive, carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. We also show an economic implementation of this adder in CMOS technology
Keywords
CMOS logic circuits; adders; asynchronous circuits; carry logic; computational complexity; delays; digital arithmetic; CMOS technology; adder speed; average computation time; delay-insensitive carry-lookahead adders; digital computer systems; economic implementation; integer addition; logic complexity; time complexity; Added delay; Adders; Asynchronous circuits; CMOS logic circuits; CMOS technology; Computer science; Counting circuits; Delay effects; Prototypes; Statistics;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location
Hyderabad
ISSN
1063-9667
Print_ISBN
0-8186-7755-4
Type
conf
DOI
10.1109/ICVD.1997.568098
Filename
568098
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