A test structure of a MOSFET with Si-implanted gate-SiO2 for EEPROM applications

The C-V and I-V characteristics of an n-MOSFET with Si-implanted gate-SiO₂ of 50 nm are analyzed by using a test device with large equal channel width and length of 100 μm, and discussed for realizing a large hysteresis window of threshold voltage. Interface trap densities change logarithmically from ~3×10¹⁰ to ~1×10¹² cm^-2 eV^-1 as the Si-dose at 25 keV increases from zero to 3×10¹⁶ cm^-2. Threshold-voltage changes caused by 25 keV implantations are as high as ±0.2 V. Effective mobilities (subthreshold swings) change from ~600 (~0.10) to ~100 cm²/V·s (~0.26 V/decade) as the Si-dose increases from 0 to 3×10¹⁶ cm^-2 at 25 keV, and both parameters are related with the change of interface trap densities. There is a close relationship between the hysteresis windows of gate current and threshold voltage, and the largest threshold voltage window in a low gate voltage region is obtained for the MOSFET with Si-implantation at 25 keV/3×10¹⁶ cm³