Modeling of test structures for efficient online defect monitoring using a digital tester

Author

Hess, Christopher ; Weiland, Larg H.

Author_Institution

Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany

fYear

1994

fDate

22-25 Mar 1994

Firstpage

108

Lastpage

113

Abstract

A novel methodology for digital measuring procedures and digital data analysis is presented in order to evaluate an online process control and defect monitoring. That can be done by manufacturing test chips side by side with standard chips and measuring them with the same measuring equipment-the digital tester. To achieve a fast and effective (efficient) measuring procedure and data analysis test structures will be modeled in geometry-graphs, neighborhood-graphs and connection-graphs

Keywords

integrated circuit testing; process control; semiconductor process modelling; test equipment; connection-graphs; digital data analysis; digital measuring procedures; digital tester; geometry-graphs; measuring procedure; neighborhood-graphs; online defect monitoring; process control; test chips; test structures; Circuit faults; Circuit testing; Computerized monitoring; Conducting materials; Data analysis; Electrical resistance measurement; Frequency measurement; Measurement standards; Process control; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1757-2

Type

conf

DOI

10.1109/ICMTS.1994.303493

Filename

303493