A 65 nm CMOS versatile ADC using time interleaving and ΣΔ modulation for multi-mode receiver

High performances wideband analog to digital converter (ADC) remains a bottleneck to realize software and cognitive radio receivers. Time interleaved sigma-delta (TISigmaDelta) architecture is a good candidate to increase the bandwidth of the data converters with the lowest hardware complexity compared to other solutions using parallel sigma-delta modulators. This paper proposes a reconfigurable 4 channels TISigmaDelta using the novel GMSCL (general multi stage closed loop) sigma-delta architecture and a new digital processing reducing considerably the hardware complexity. The sigma-delta modulators have been designed using switched-capacitor technique and implemented with STMicroelectronis 65 nm CMOS technology. Three different scenarios are possible : the first one for GSM standard clocked at 26 MHz and consumes 2.59 mW, the second one for UMTS/DVB-T standards clocked at 208 MHz and consumes 46 mW and the last one for WiFi/WiMax standards clocked at 208 MHz and consumes 92 mW. The total circuit die area is equal to 3 mm². The digital filtering was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. For a clock rate of 208 MHz, the evaluated die area is 0.115 mm².