Modeling and enhancing virtual memory performance in logic simulation

To achieve acceptable performance, virtual memory systems generally rely on the presence of a high degree of spatial and temporal reference locality during code execution. The enormous quantity of intricately related data typically found in logic simulation makes this a dubious assumption. There simply is no way to statically organize circuit representation data to ensure locality. This phenomenon is explored through the analysis of address reference data obtained from a logic tester monitoring simulation execution on a general-purpose virtual memory workstation. Data from code compilation runs are included to illustrate the differences in reference behavior found between logic simulation and more conventional applications. An improved virtual memory management scheme based on speculative references and tuned to logic simulation is presented.<>