Design and implementation of an embedded 512KB level 2 cache subsystem

Author

Shin, Jinuk Luke ; Petrick, Bruce ; Levy, Howard ; Son, Jinseung ; Singh, Mandeep ; Mathur, Vikas ; Yeh, Jung-Cheng ; Choi, Heesung ; Gupta, Vishal ; Ziaja, Tom ; Leon, Ana Sonia

Author_Institution

Sun Microsystems Inc., Sunnyvale, CA, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

349

Lastpage

352

Abstract

Dual on-chip 512 kB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13 μm technology. Each 512 kB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 13 V and 85 C. This fully integrated subsystem is composed of data and tag SRAMs along with datapaths, controller and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64b microprocessors, with a data latency of only 4 cycles including ECC correction for 128-bit data. The design solutions to build this integrated short latency L2 cache are discussed.

Keywords

SRAM chips; cache storage; integrated circuit design; integrated circuit testing; microprocessor chips; 0.13 micron; 1.3 V; 1.4 GHz; 128 bit; 2.6 W; 512 KB; 64 bit; 85 C; ECC correction; UltraSparc processor; controller; data SRAM; data latency; datapaths; dual on-chip unified second level caches; embedded level two cache subsystem design; fully integrated subsystem; integrated short latency L2 cache design; on-chip L2 cache latency; tag SRAM; test engines; Clocks; Delay; Engines; Frequency; Logic; Microprocessors; Pipelines; Protection; Random access memory; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358818

Filename

1358818