• DocumentCode
    1949651
  • Title

    SOI and device scaling

  • Author

    Hu, C.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1998
  • fDate
    5-8 Oct. 1998
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In the past five years, impressive progress has been made in SOI materials, device and process demonstrations, and product research, yet SOI IC technology remains a promise more than a reality. An important reason is that the rate of bulk technology scaling, in terms of gate length, gate oxide thickness, threshold voltage (V/sub t/), and performance has exceeded earlier expectations (Hu, 1995). In an environment of rapidly advancing bulk technology, it was difficult to overcome the concern over the known and unknown risks of adopting SOI technology, as it was not known how the situation might change with future scaling. This paper attempts to highlight some considerations in three phases of device scaling-when bulk device scaling may proceed rapidly, slowly, and with extreme difficulty.
  • Keywords
    dielectric thin films; integrated circuit design; integrated circuit technology; silicon-on-insulator; SOI; SOI IC technology; SOI device scaling; SOI devices; SOI materials; SOI processing; SOI product research; SOI technology; Si-SiO/sub 2/; bulk device scaling difficulty; bulk technology; bulk technology scaling; device scaling; gate length; gate oxide thickness; rapid bulk device scaling; slow bulk device scaling; threshold voltage; Capacitance; Circuit optimization; Circuit synthesis; Costs; Degradation; Design optimization; Integrated circuit interconnections; Investments; MOSFETs; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 1998. Proceedings., 1998 IEEE International
  • Conference_Location
    Stuart, FL, USA
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-4500-2
  • Type

    conf

  • DOI
    10.1109/SOI.1998.723043
  • Filename
    723043