• DocumentCode
    1949700
  • Title

    Experiments in logic optimization

  • Author

    Lightner, M. ; Wolf, W.

  • Author_Institution
    Colorado Univ., Boulder, CO, USA
  • fYear
    1988
  • fDate
    7-10 Nov. 1988
  • Firstpage
    286
  • Lastpage
    289
  • Abstract
    A number of experiments have been conducted to answer several important questions about logic optimization and its application to high-level synthesis. The experiments are summarised and show that: logic optimization is competitive with manual design; stronger optimization methods give somewhat better average results (10%-30%) at much greater computational cost (8* and more); fast logic optimization methods can be used to estimate the average results of the more powerful, costly methods; and literal count is a good estimator of area before routing for standard cell designs.<>
  • Keywords
    logic CAD; performance evaluation; computational cost; high-level synthesis; literal count; logic optimization; manual design; optimization experiments; optimization methods; standard cell designs; Boolean functions; Design optimization; Hardware; High level synthesis; Libraries; Logic circuits; Logic design; Logic functions; Optimization methods; Optimizing compilers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-0869-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.1988.122512
  • Filename
    122512