EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents

The lossy silicon substrate has significant effects on the already complicated interconnect modeling issue. To account for the substrate loss, traditional electromagnetic methods are often computationally prohibitive for large scale VLSI geometries. In this paper, we present EPEEC (eddy-current-aware partial equivalent element circuit) which extends the traditional PEEC model to consider substrate eddy current loss, based on complex image theory and skin and proximity effects, by discretization of conductors. To deal with an even larger scale of interconnects, we enhance the EPEEC model to use reluctance by equipping it with an advanced windowing algorithm to further reduce the model size and runtime. Detailed comparisons with state-of-the-art tools such as FastHenry and Momentum demonstrate that EPEEC is within 1% accuracy while providing over 100× speedup.