LogTOTEM: A Logarithmic Neural Processor and its Implementation on an FPGA Fabric

This paper describes the design of a neural network architecture optimised for use with the reactive Tabu search (RTS) training algorithm. The neural network is built using the hybrid-logarithmic number system (hybrid-LNS) instead of the traditional fixed-point methods for the multiply-accumulate (MAC) unit contained in each neuron. The circuits have been designed and implemented using between 4 and 8 bits of fractional precision for the logarithmic representation of the weights and the data. The architecture is based on the existing TOTEM VLSI chip and contains 32 neurons each having a 256 times 10-bit weight RAM. The device has been implemented on a Virtex XCV600 device where it consumed less 6025 slices with 4 bits of fractional precision of the logarithms and 6280 slices with 5 bits of fractional precision. At 4-bits This represents a (45%) reduction in logic resources required by the neuron array and an overall reduction of 10% of the FPGA resources when compared to the SoftTOTEM device built using the same technology.