DocumentCode
1950789
Title
Testing of a low inductance stacked mosfet switch for Pulsed Ring Down Sources
Author
Reale, D. ; Mankowski, J. ; Holt, S. ; Walter, J. ; Dickens, J.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Tech Univ., Lubbock, TX, USA
fYear
2011
fDate
19-23 June 2011
Firstpage
1124
Lastpage
1127
Abstract
An inexpensive and mobile array of Pulsed Ring Down Sources (PRDS) were required to verify previous simulation results. Initial attempts to use a stacked MosFET circuit as a closing switch were unsuccessful due to the additional series inductance of the MosFET stack lowering the frequency of the oscillation on the coaxial radiator. Experimental results showed that by reducing the parasitic inductance due to the geometry of the MosFET stack, the frequency of the oscillation could be increased. Increased series resistance due to the stacked MosFETs was also a concern. In order to minimize the parasitic inductance of the stack and allow for multiple stacks to be connected in parallel, a printed circuit board was designed. Results from testing of the original switch stacks and board assembly are presented and compared with PSPICE simulations. Using the simulation results, the reduction in parasitic inductance can be estimated.
Keywords
SPICE; field effect transistor switches; simulation; PRDS; PSPICE; coaxial radiator; low inductance stacked MOSFETswitch; pulsed ring down sources; simulation; testing; Assembly; Global Positioning System; Power MOSFET; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Pulsed Power Conference (PPC), 2011 IEEE
Conference_Location
Chicago, IL
ISSN
2158-4915
Print_ISBN
978-1-4577-0629-5
Type
conf
DOI
10.1109/PPC.2011.6191656
Filename
6191656
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