Integration of power LDMOS into a low-voltage 0.5 mu m BiCMOS technology

Author

Tsui, P.G.Y. ; Gilbert, P.V. ; Shih Wei Sun

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

27

Lastpage

30

Abstract

Integration of a power Lateral Double Diffused MOS (LDMOS) structure into a high performance 0.5 mu m BiCMOS technology for high density, multi-functional integrated circuit (IC) applications is described. The advantages of VLSI processing and rules have been applied to the design and the manufacturing of the high density LDMOS without sacrificing the performance of 0.5 mu m dual-poly (n/sup +//p/sup +/) gate CMOS and polysilicon emitter bipolar (f/sub T/=26 GHz) transistors. The measured source to drain on-state resistance of the fabricated LDMOS is 90 m Omega -mm/sup 2/. Further device optimization, by means of 2D numerical simulations, can increase the breakdown voltage of the LDMOS to 60 V using this technology.<>

Keywords

BiCMOS integrated circuits; VLSI; electric breakdown of solids; integrated circuit technology; power integrated circuits; 0.5 micron; 60 V; VLSI processing; breakdown voltage; device optimization; dual-poly gate CMOS; lateral double diffused MOS; low-voltage BiCMOS technology; multi-functional integrated circuit; polysilicon emitter bipolar transistors; power LDMOS; source to drain on-state resistance; BiCMOS integrated circuits; Electric breakdown; Integrated circuit fabrication; Power integrated circuits; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307301

Filename

307301