Nanocleaving: an enabling technology for ultra-thin SOI

Author

Current, M.I.

Author_Institution

Silicon Genesis Corp., San Jose, USA

fYear

2002

fDate

2-3 Dec. 2002

Firstpage

Lastpage

101

Abstract

The principal features of CMOS transistor scaling into the SOI-era and the key steps of the Silicon Genesis SOI wafer fabrication technologies are outlined. Results for ultra-thin SOI wafers, with near and sub-Angstrom surface roughness over lateral scales up to 10 /spl mu/m and device layer thickness uniformity range (max-min) of /spl sim/5%, are presented for 200 and 300 mm SOI wafers. Some of the implications of SOI-CMOS scaling for ion implantation doping and SOI wafer fabrication are considered.

Keywords

CMOS analogue integrated circuits; MOSFET; elemental semiconductors; ion implantation; semiconductor doping; silicon-on-insulator; surface roughness; 200 mm; 300 mm; SOI-CMOS transistor scaling; Si; enabling technology; ion implantation doping; nanocleaving; silicon genesis SOI wafer fabrication; silicon on insulator wafer; surface roughness; ultrathin SOI wafers fabrication; CMOS technology; Dielectrics; Doping; Etching; Fabrication; Rough surfaces; Silicon; Thickness control; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on

Conference_Location

Tokyo, Japan

Print_ISBN

4-89114-028-3

Type

conf

DOI

10.1109/IWJT.2002.1225214

Filename

1225214

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1951624