Implementation of Advance Encryption Standard algorithm on FPGA for the protection of Remote Sensing Satellite

Advanced Encryption Standard (AES) and state of art technology FPGAs (Field Programmable Gate Arrays) can be used together to mitigate the potential threats of interception of Satellite data and unauthorized access to the Satellite System. This paper discusses the implementation and verification of AES algorithm on Virtex 4 FPGA and its usage in the protection of Remote Sensing Satellite Data. The performance of the designed core has been verified by the Timing Simulation, on Chip Debugging and through Synthesized report. The analysis of designed core shows that this core can give throughput of 1579 Mbps and take less than 6 % resources of the FPGA, which make it suitable to be use in Remote Sensing Satellite.