An incremental approach for test scheduling and synthesis using genetic algorithms

Author

Harmanani, Haidar ; Hajar, Aouni

Author_Institution

Dept. of Comput. Sci., Lebanese American Univ., Byblos, Lebanon

fYear

2004

fDate

20-23 June 2004

Firstpage

69

Lastpage

72

Abstract

This paper presents a new and an efficient method for concurrent BIST synthesis and test scheduling. This method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and multiplexers. The method is based on a genetic algorithm that efficiently explores the testable design space. The method was implemented using C++ on a Linux workstation. Several benchmark examples have been implemented and favorable results are reported.

Keywords

C++ language; Linux; built-in self test; circuit optimisation; genetic algorithms; high level synthesis; integrated circuit testing; logic testing; multiplexing equipment; shift registers; C++ language; Linux; concurrent BIST synthesis; concurrent testing; genetic algorithms; high level synthesis; integrated circuit testing; multiplexers; test registers; test scheduling; Automatic testing; Biological cells; Built-in self-test; Circuit testing; Digital circuits; Genetic algorithms; High level synthesis; Performance evaluation; Processor scheduling; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on

Print_ISBN

0-7803-8322-2

Type

conf

DOI

10.1109/NEWCAS.2004.1359019

Filename

1359019