Low-energy design of a 3G-compliant turbo decoder

In this work, a rate-1/3 8-state log-MAP turbo decoder for third-generation wireless terminals is designed. Several architectural and logic level techniques are applied to reduce area and power, and increase throughput of the turbo decoder. Furthermore, an efficient dynamic-iterative technique, reliable at both poor and good channel conditions, is applied for additional power reduction of the turbo decoder. After modeling the turbo decoder in VHDL, it is synthesized and optimized into 0.18 μ CMOS standard cells. The gate-level design has an estimated core area of about 0.58 mm². The turbo decoder works at a maximum clock frequency of 100 MHz, and with an upper limit of 5 iterations, it achieves a 5 Mb/s data rate and consumes about 50 mW of power. Hence, the designed turbo decoder has an energy efficiency of 2 nJ/b/iteration.