3-D finite elements simulation of drop test reliability on a Chip Scale Package: Focus on the component architecture and materials

Chip Scale Package (CSP) fulfills the demand for small, light and portable handheld electronic devices and is one of the most advanced packaging concepts. Reliability of this package becomes more critical since their solder joins endure harsh mechanical loads such as drop impact during transportation or operations. Cracking of solder interconnections is often caused by excessive bending of circuit board subject to input acceleration created from dropping handled electronic products. It is known that the dynamic strains and stress states of solder bumps directly affect their reliability during drop impact. In this paper, 3-D finite-elements calculations have been carried out to analyze the effects of chip thickness, Through-Silicon-Vias TSV dimensions and material properties on a new 3D chip scale package (CSP) behavior during an impact. TSVs distribution effect is discussed, two cases have been modeled : bumps located on TSVs and bumps located with an offset in regards with TSV s position. The behavior under shock loading conditions has been analyzed to determine the stress and strain concentration areas. These numerical results will be exploited in fatigue prediction law. Numerical results show that the maximum plastic strain in the bump decreases with the chip thickness. For 0.1 mm Silicon thickness, stress and strain localization and amplitude depend on the TSVs distributions. Bumps on TSVs configuration leads to stress concentration areas around and between VIAs. In the second configuration stress concentration areas are minimized. A comparison between Copper and PolySilicon VIAs shows that the second material gives better results in terms of plastic deformation. In all configurations, the critical position is localized, as expected, at the corner bump.