DocumentCode
1952355
Title
A novel asynchronous wrapper using 1-of-4 data encoding and single-track handshaking
Author
Upadhyay, Adhir ; Hasan, Syed Rafay ; Nekili, Mohamed
Author_Institution
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
fYear
2004
fDate
20-23 June 2004
Firstpage
205
Lastpage
208
Abstract
Globally asynchronous locally synchronous (GALS) design style has evolved as a solution to increasing problems of distributing clock at high frequency in DSM technology. Most wrapper designs proposed in some recent literature are based on bundled data protocols and suffer from the same timing closure problem as synchronous designs. Delay insensitive (DI) protocols offer a solution to this problem. However, most of the work on DI schemes was limited to asynchronous circuits so far. This is, to our knowledge, the first paper that presents a complete asynchronous wrapper architecture for GALS designs based on a DI protocol. It uses 1-of-4 data encoding with single-track handshaking. The resulting circuit shows a throughput of 1.66 Gbps, significantly higher than previous asynchronous DI templates.
Keywords
CMOS integrated circuits; asynchronous circuits; clocks; encoding; integrated circuit design; logic design; pipeline processing; protocols; CMOS integrated circuits; asynchronous circuits; asynchronous wrapper architecture; bundled data protocols; data encoding; deep submicron technology; delay insensitive protocols; distributing clock; globally asynchronous locally synchronous design; integrated circuit design; pipeline processing; single track handshaking; Asynchronous circuits; CMOS technology; Clocks; Delay; Encoding; Integrated circuit interconnections; Pipelines; Protocols; Timing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN
0-7803-8322-2
Type
conf
DOI
10.1109/NEWCAS.2004.1359062
Filename
1359062
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