Modeling in Verilog-AMS of a front-end for the design of a multichannel readout ASIC for Si microstrips

Verilog-AMS is used to model the analog front-end of one channel in a multichannel readout ASIC for Silicon microstrips. The modelization in a behavioral language allowed to extract the requirements of the main components of the channel without needing to make the design at transistor level, thus decreasing the design time. This model of a complete channel will be used for further integration with the digital processing electronics of the multichannel ASIC.