Efficient implementation of CIOQ switches with sequential iterative matching algorithms

This paper presents the implementation of a crossbar-based CIOQ switch with a novel matching algorithm that can be used for efficient interprocessor communication. The proposed matching algorithm, called SIM, uses a sequential mode to replace the traditional parallel mode to improve the efficiency of iterative matching operation. Moreover, the paper presents a FIFO-based request scheduler for the implementation of SIM. The proposed algorithm and its implementation architecture are evaluated in an FPGA. The implementation-based simulation results show that for switches without speedup, SIM can achieve higher aggregate throughput and lower average delay than iSLIP. Moreover, SIM achieves a fair trade-off among performance and logic area.