DocumentCode
1952710
Title
Elimination of bipolar-induced breakdown in fully-depleted SOI MOSFETs
Author
Ver Ploeg ; Watanabe, T. ; Kistler, N.A. ; Woos, J.C.S. ; Plummer, J.D.
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
fYear
1992
fDate
13-16 Dec. 1992
Firstpage
337
Lastpage
340
Abstract
N-channel SOI MOSFETs suffer from low breakdown voltages due to the existence of an inherent parasitic n-p-n bipolar transistor. In this work we introduce a new device structure, the dual source SOI MOSFET (DSFET) that eliminates the effects of the parasitic BJT. We also present measured and simulated results of the device demonstrating its effectiveness and illustrating its operation.<>
Keywords
bipolar transistors; electric breakdown of solids; insulated gate field effect transistors; semiconductor technology; semiconductor-insulator boundaries; N-channel SOI MOSFET; bipolar-induced breakdown; breakdown voltages; dual source SOI MOSFET; effectiveness; fabrication; fully-depleted SOI MOSFET; inherent parasitic n-p-n bipolar transistor; Bipolar transistors; Electric breakdown; Insulated gate FETs; Semiconductor device fabrication; Semiconductor-insulator interfaces;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-0817-4
Type
conf
DOI
10.1109/IEDM.1992.307373
Filename
307373
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