ISDN echo cancellation circuit (IEC), a transceiver for the subscriber loop

Author

Niggebaum, R. ; Vogel, D. ; Schenk, H.

Author_Institution

Siemens AG, Stuttgart, West Germany

fYear

1988

fDate

7-9 June 1988

Firstpage

853

Abstract

The digital part of a two-chip U-interface transceiver for the subscriber loop is presented. According to the ISDN (integrated-services digital network) standard all communication control and algorithmic requirements are implemented for a 144-kb/s full duplex data transmission. The chip is implemented in a double-metal 2- mu m CMOS technology with an area of 8.2 mm*7.3 mm containing 58000 transistors, 15000 of which are implemented in a cell approach, the rest in hand-tuned digital signal processor.<>

Keywords

CMOS integrated circuits; ISDN; VLSI; digital integrated circuits; digital signal processing chips; echo suppression; logic arrays; 144 kbit/s; 144-kb/s full duplex data transmission; 2 micron; 7.3 to 8.2 mm; IEC; ISDN echo cancellation circuit; VLSI; cellular array; digital part; digital subscriber line transceivers; double metal CMOS; hand-tuned digital signal processor; integrated-services digital network; subscriber loop; two-chip U-interface transceiver; CMOS technology; Circuits; Communication standards; Communication system control; Echo cancellers; IEC; ISDN; Signal processing algorithms; Subscriber loops; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.15057

Filename

15057