Phasor-assisted automated topology processing for state estimators

This article provides a robust network topology processor for state estimators that utilizes both conventional and/or PMU measurements. The emphasis is on the involvement of PMU measurements in topology processing. Building on top of the state of the art, an algorithm is proposed in a way to cover the limitations of current approaches and at the same time to suggest new features. The topology processor was coded in MATLAB and is tested using a modified version of the IEEE Reliability Test System 1996. The topology processor is intended to provide network topologies to PMU-only sate estimators, so the test system is simulated in real-time using the eMegaSim Opal-RT real-time simulator that generates synthetic data mimicking a real PMU. Different test scenarios are carried out and the topology processor efficiency and robustness is verified by the test results. Specifically, it is testified through a discussion that the proposed method is fast enough to support PMU-only state estimators, as well as conventional or phasor-assisted state estimators.