Pipeline-level control of self-resetting stage pipelines

In this paper, we present a novel synchronization approach to support data flow in clockless designs using single-rail encoding. This approach is based on self-resetting stage logic in which a pipeline stage resets itself before starting the next execution cycle. As such, a stage goes through a reset phase when its output is , and an evaluate phase when its output is the result of the evaluation of its inputs. To insure proper operation, a latch-based synchronization mechanism is proposed which yields an efficient and a simple uni-directional handshaking scheme emanating from the last stage in the pipeline back towards the remaining stages of the pipeline. A concept design of a four-bit 16-stage pipeline is presented to illustrate the inner workings of self-resetting stage logic and its data-flow synchronization mechanism controlled at pipeline level. The overall pipeline´s performance is elucidated through a detailed signal timing analysis to bring to light how the duration of the evaluate phase, reset phase, and the latch enable of a given stage depends on its location within the pipeline.