DocumentCode
1953616
Title
Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation
Author
Minami, E.R. ; Quader, K.N. ; Ko, P.K. ; Chenming Hu
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1992
fDate
13-16 Dec. 1992
Firstpage
539
Lastpage
542
Abstract
We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits. The use of a timing simulator enables a quick characterization of degradation in large circuits. The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude.<>
Keywords
CMOS integrated circuits; VLSI; circuit analysis computing; digital integrated circuits; digital simulation; hot carriers; semiconductor device models; IRSIM-CAS; RC time-constant; digital CMOS VLSI; digital CMOS circuits; hot-carrier degradation; timing simulation; CMOS integrated circuits; Circuit simulation; Digital integrated circuits; Hot carriers; Semiconductor device modeling; Simulation; Very-large-scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-0817-4
Type
conf
DOI
10.1109/IEDM.1992.307419
Filename
307419
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