3D deformation FEM simulations and measurement during VDMOS transistor operation

Author

Marcault, E. ; Weidmann, D. ; Bourennane, A. ; Breil, M. ; Charpiot, L.

Author_Institution

LAAS, Toulouse, France

fYear

2012

fDate

16-18 April 2012

Firstpage

42373

Lastpage

42464

Abstract

This paper deals with the reliability of power device assembly. We make use of 3D electro-thermo-mechanical simulations tools to highlight the power chip deformation during its conducting state. Moreover, we carry out experimental deformation measurement using a T.D.M^® (Topography and Deformation Measurement) equipment. These simulations and measurements could allow to evaluate the reached mechanical stress level in a power assembly (in the different materials and at the different interfaces) during power device operation.

Keywords

assembling; deformation; finite element analysis; integrated circuit reliability; power MOSFET; 3D deformation FEM simulation; 3D electro-thermo-mechanical simulations tool; VDMOS transistor operation; experimental deformation measurement; mechanical stress level evaluation; power chip deformation; power device assembly reliability; power device operation; topography; Aluminum; Finite element methods; Joints; MOSFET circuits; Semiconductor device measurement; Thermal expansion; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2012 13th International Conference on

Conference_Location

Cascais

Print_ISBN

978-1-4673-1512-8

Type

conf

DOI

10.1109/ESimE.2012.6191781

Filename

6191781