Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?

Author

Frank, D.J. ; Laux, S.E. ; Fischetti, M.V.

Author_Institution

Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

553

Lastpage

556

Abstract

Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling. This dual-gated 30 nm gate-length FET is found to have excellent characteristics for use in digital logic, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps. The various motivations for this device design are discussed, illuminating the reasons for claiming that it is at the limits of scaling.<>

Keywords

Monte Carlo methods; digital integrated circuits; digital simulation; elemental semiconductors; field effect transistor circuits; insulated gate field effect transistors; integrated circuit technology; semiconductor device models; silicon; 1.1 ps; 30 nm; Monte Carlo simulation; Si; digital logic; dual-gate MOSFET; n-channel MOSFET; ring-oscillator delay; scaling; transconductance; Digital integrated circuits; FET circuits; Insulated gate FETs; Integrated circuit fabrication; Monte Carlo methods; Semiconductor device modeling; Silicon; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307422

Filename

307422