Towards fully integrated SiC cascade power switches for high voltage applications

Author

Mihaila, A. ; Udrea, F. ; Godignon, P. ; Brezeanu, G. ; Malhan, R.K. ; Rusu, A. ; Millan, J. ; Amaratunga, G.

Author_Institution

Eng. Dept., Cambridge Univ., UK

fYear

2003

fDate

14-17 April 2003

Firstpage

379

Lastpage

382

Abstract

This paper presents an advanced numerical analysis of novel hybrid silicon/SiC multiple cascode configuration. The novel approach is exemplified through a three device cascode Configuration, whereby a 5-20V silicon MOSFET blocks a lateral medium voltage 60-100V SiC JFET, which in turn reverse biases the gate of a vertical high voltage (≥1.2kV) SiC JFET. Furthermore, an elegant solution for the SiC part of the hybrid multiple cascode is also presented. A fully integrated SiC cascoded JFETs chip is proposed and numerically demonstrated. The results obtained through mixed mode simulations for the two cascode configurations are compared.

Keywords

JFET integrated circuits; MOSFET; numerical analysis; power semiconductor switches; silicon compounds; wide band gap semiconductors; 1.2 kV; 5 to 20 V; 60 to 100 V; SiC JFET; SiC multiple cascode configuration; cascade power switches; high voltage applications; integrated SiC; mixed mode simulations; numerical analysis; silicon MOSFET; three device cascode configuration; Capacitance; JFET circuits; Laboratories; MOSFET circuits; Medium voltage; Numerical analysis; Power MOSFET; Protection; Silicon carbide; Transient response;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on

Print_ISBN

0-7803-7876-8

Type

conf

DOI

10.1109/ISPSD.2003.1225306

Filename

1225306