• DocumentCode
    1954747
  • Title

    High-efficiency Lattice QCD computations on the Fermi architecture

  • Author

    Clark, M.A. ; Babich, R.

  • Author_Institution
    NVIDIA Corp., Santa Clara, CA, USA
  • fYear
    2012
  • fDate
    13-14 May 2012
  • Firstpage
    1
  • Lastpage
    9
  • Abstract
    Lattice Quantum Chromodynamics (LQCD) is a computationally challenging problem that solves the discretized Dirac equation in the presence of an SU(3) gauge field. The most time-consuming computational routine is the application of the discretized Dirac operator (a sparse matrix) to a vector. GPUs have proven to be a popular platform on which to deploy such computations; however, because of the relatively low arithmetic intensity (flop-to-byte ratio) of this “Dslash” operation, it is hard to realize a significant fraction of peak performance. Like many other stencil-based computations, the Dslash operation exhibits spatial locality, which can be used to minimize memory traffic and hence increase achievable performance. In this work we present a cache-blocking strategy which is suited to the relatively limited amount of cache on current-generation GPUs. We present results on NVIDIA´s Fermi architecture for the Wilson discretization, demonstrating performance in excess of 300 Gflops in single precision, which corresponds to 79% of the peak achievable assuming perfect reuse (i.e., an infinite cache). Finally, we speculate on how one might improve on this performance through finer-grained parallelization and temporal cache blocking.
  • Keywords
    Dirac equation; cache storage; graphics processing units; lattice theory; matrix algebra; quantum chromodynamics; quantum computing; Dslash operation; NVIDIA fermi architecture; SU(3) gauge field; Wilson discretization; cache-blocking strategy; computational routine; current-generation GPU; discretized Dirac equation; finer-grained parallelization; flop-to-byte ratio; high-efficiency lattice QCD computations; lattice quantum chromodynamics; memory traffic minimization; sparse matrix; temporal cache blocking; Abstracts; Lead; Load modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative Parallel Computing (InPar), 2012
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4673-2632-2
  • Electronic_ISBN
    978-1-4673-2631-5
  • Type

    conf

  • DOI
    10.1109/InPar.2012.6339591
  • Filename
    6339591