• DocumentCode
    1956004
  • Title

    FIFO Design for IEEE 802.3 Standard 10GBase-X PCS and XGXS Sublayers

  • Author

    Thayaparan, S. ; Nanayakkara, A.

  • Author_Institution
    Dept. of Electron. & Telecommun. Eng., Univ. of Moratuwa, Morituwa, Sri Lanka
  • fYear
    2013
  • fDate
    29-31 Jan. 2013
  • Firstpage
    589
  • Lastpage
    591
  • Abstract
    This paper analyses the FIFO design for the receiver of 10GBase-X PCS sublayers specified by IEEE 802.3 CSMA/CD Standards. The proposed FIFO design will save the gate count, power and the silicon area in ASIC design considerably.
  • Keywords
    application specific integrated circuits; carrier sense multiple access; wireless LAN; 10Gbase-X PCS; ASIC design; FIFO design; IEEE 802.3 CSMA-CD standards; XGXS sublayers; bit rate 10 Gbit/s; silicon area; Clocks; EPON; IEEE 802.3 Standards; Random access memory; Receivers; Registers; Synchronization; FIFO Design; CSMA/CD standards; IEEE 802.3; clock rate compensation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Intelligent Systems Modelling & Simulation (ISMS), 2013 4th International Conference on
  • Conference_Location
    Bangkok
  • ISSN
    2166-0662
  • Print_ISBN
    978-1-4673-5653-4
  • Type

    conf

  • DOI
    10.1109/ISMS.2013.125
  • Filename
    6498339
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1956004