Multiple data set reduction on FPGAs

Many scientific or engineering applications perform reduction of sets of sequential data streams. If the core operator of the reduction is deeply pipelined, dependencies between the input data elements cause data hazards in the pipeline. To tackle this problem, we propose a multiple set variable length reduction design with low latency and high pipeline utilization in this paper. We prove the buffer size and execution time bounds, and then show its performance on practical multiple data set scenarios. We apply the proposed method to the Householder QR decomposition and compare its performance to other methods with superior results. The proposed design is implemented on FPGAs with resource usage and performance presented.