A VLSI architecture for multiplication, division and square root

Author

McQuillan, S.E. ; McCanny, J.V.

Author_Institution

Inst. of Adv. Microelectron., Queen´´s Univ. of Belfast, UK

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1205

Abstract

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable

Keywords

VLSI; computerised signal processing; digital arithmetic; pipeline processing; 80 MIPS; CMOS technology; VLSI architecture; division; execution time; minimal control; multiplication; pipelining; redundancy; square root; throughput rates; Algorithm design and analysis; Arithmetic; CMOS technology; Circuits; Digital signal processing; Hardware; Microelectronics; Signal processing algorithms; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150600

Filename

150600

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1957772