DocumentCode
1961309
Title
Design of moore finite state machine with extended state codes
Author
Titarenko, Larysa ; Hebda, Olena ; Barkalov, Alexander
Author_Institution
Inst. of Comput. Eng. & Electron., Univ. of Zielona Gora, Zielona Gora, Poland
fYear
2013
fDate
24-27 June 2013
Firstpage
347
Lastpage
352
Abstract
The new method is proposed for reduction of chip area occupied by logic circuit of Moore FSM implemented with PLAs. It is based on the representation of the state code as a concatenation of the code of class of pseudoequivalent states and code of state inside this class. Such an approach allows elimination of dependence among states and output variables. It allows the hardware reduction in the FSM logic circuit in comparison with known design methods.
Keywords
finite state machines; logic circuits; logic design; FSM logic circuit; Moore finite state machine design; PLA; chip area reduction; code concatenation; extended state codes; hardware reduction; pseudoequivalent states; Design methodology; Encoding; Hardware; Integrated circuit modeling; Minimization; Programmable logic arrays; Moore FSM; PLA; area reduction; pseudoequivalent states;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology Interfaces (ITI), Proceedings of the ITI 2013 35th International Conference on
Conference_Location
Cavtat
ISSN
1334-2762
Print_ISBN
978-953-7138-30-1
Type
conf
DOI
10.2498/iti.2013.0504
Filename
6649051
Link To Document