DocumentCode
1961923
Title
Packet multiplexing: an efficient router implementation for adaptive mesh networks
Author
Izu, C. ; Beivide, R. ; Arruabarrena, A. ; Gregorio, J.A.
Author_Institution
Konputagailuen Arkitektura eta Teknologia Saila, Euskal Herriko Unibertsitatea, Donostia, Spain
Volume
2
fYear
1995
fDate
19-21 Apr 1995
Firstpage
603
Abstract
The performance of an interconnection network with adaptive routing is strongly related to the deadlock avoidance method it applies. Virtual channels are normally used for this purpose in mesh and torus networks. This work compares true architectural alternatives in the router design: mapping each virtual channel onto a different physical link and multiplexing the set of virtual channels onto the same physical link. Besides, multiplexing at the packet level is proposed as an alternative to multiplexing at the flit level, showing the advantages of this not previously used approach. The benefits of each multiplexing type, both in message latency and throughput, have been evaluated under several traffic conditions. An estimation of the node delay for each implementation scheme has also been calculated
Keywords
multiprocessor interconnection networks; packet switching; parallel architectures; reconfigurable architectures; adaptive mesh networks; deadlock avoidance method; efficient router implementation; interconnection network; message latency; node delay; packet multiplexing; throughput; Adaptive systems; Augmented virtuality; Costs; Delay estimation; Mesh networks; Network topology; Routing; System recovery; Telecommunication traffic; Time of arrival estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on
Conference_Location
Brisbane, Qld.
Print_ISBN
0-7803-2018-2
Type
conf
DOI
10.1109/ICAPP.1995.472247
Filename
472247
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